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| SPANSION Flash Memory Data Sheet TM September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-20886-3E FLASH MEMORY CMOS 64M (4M x 16) BIT MBM29LV652UE90 s GENERAL DESCRIPTION The MBM29LV652UE is a 64M-bit, 3.0 V-only Flash memory organized as 4M words of 16 bits each. The device is designed to MBM29LV652UE be programmed in system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29LV652UE is entirely command set compatible with JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Typically, each sector can be programmed and verified in about 0.5 seconds. s PRODUCT LINE UP Part No. Power Supply Voltage (V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MBM29LV652UE90 VCC = 3.3 V -0.3 V 90 90 35 +0.3 V s PACKAGE 63-ball plastic FBGA (BGA-63P-M02) MBM29LV652UE90 (Continued) A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV652UE is erased when shipped from the factory. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. The devices electrically erase all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The words are programmed one word at a time using the EPROM programming mechanism of hot electron injection. s FEATURES * 0.23 m Process Technology * Single 3.0 V read, program and erase Minimizes system level power requirements * Compatible with JEDEC-standards Uses same software commands with single-power supply Flash * Address don't care during the command sequence * Industry-standard pinouts 63-ball FBGA (Package suffix: PBT) * Minimum 100,000 program/erase cycles * High performance 90 ns maximum access time * Flexible sector architecture One hundred twenty-eight 32K word sectors Any combination of sectors can be concurrently erased. Also supports full chip erase * HiddenROM region 128 word of HiddenROM, accessible through a new "HiddenROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion * ACC input pin At VACC, increases program performance * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded programTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * Sector group protection Hardware method disables any combination of sector groups from program or erase operations * Sector Group Protection Set function by Extended sector protect command * Fast Programming Function by Extended Command (Continued) 2 MBM29LV652UE90 (Continued) * Temporary sector group unprotection Temporary sector group unprotection via the RESET pin This feature allows code changes in previously locked sectors * In accordance with CFI (Common Flash Memory Interface) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29LV652UE90 s PIN ASSIGNMENT FBGA (TOP VIEW) Marking Side A8 N.C. B8 N.C. L8 N.C. M8 N.C. A7 N.C. B7 N.C. C7 A13 D7 A12 E7 A14 F7 A15 G7 A16 H7 Vccq J7 DQ15 K7 Vss L7 N.C. M7 N.C. C6 A9 D6 A8 E6 A10 F6 A11 G6 DQ7 H6 DQ14 J6 DQ13 K6 DQ6 C5 WE D5 RESET E5 A21 F5 A19 G5 DQ5 H5 DQ12 J5 Vcc K5 DQ4 C4 RY/BY D4 ACC E4 A18 F4 A20 G4 DQ2 H4 DQ10 J4 DQ11 K4 DQ3 C3 A7 D3 A17 E3 A6 F3 A5 G3 DQ0 H3 DQ8 J3 DQ9 K3 DQ1 A2 N.C. C2 A3 D2 A4 E2 A2 F2 A1 G2 A0 H2 CE J2 OE K2 Vss L2 N.C. M2 N.C. A1 N.C. B1 N.C. L1 N.C. M1 N.C. (BGA-63P-M02) * : Peripheral balls on each corner are shorted together via the substrate but not connected to the die. 4 MBM29LV652UE90 s PIN DESCRIPTION Pin A21 to A0 DQ15 to DQ0 CE OE WE RY/BY RESET ACC VCCq N.C. VSS VCC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection Program Acceleration Output Buffer Power No Internal Connection Device Ground Device Power Supply Function 5 MBM29LV652UE90 s BLOCK DIAGRAM RY/BY Buffers VCC VSS RY/BY DQ15 to DQ0 Erase Voltage Generator Input/Output Buffers VCCq WE RESET ACC State Control Command Register Program Voltage Generator CE OE Chip Enable Output Enable Logic STB Data Latch STB Y-Decoder Y-Gating Timer for Program/Erase Address Latch X-Decoder Cell Matrix A21 to A0 6 MBM29LV652UE90 s LOGIC SYMBOL 22 A21 to A0 DQ15 to DQ0 CE OE WE RESET ACC RY/BY 16 VCCq 7 MBM29LV652UE90 s DEVICE BUS OPERATION MBM29LV652UE User Bus Operations Table Operation Auto-Select Manufacture Code *1 Auto-Select Device Code *1 Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Group Protection *2 *4 Verify Sector Group Protection *2 *4 Temporary Sector Group Unprotection *5 Reset (Hardware)/Standby Legend: L = VIL, H = VIH, X = VIL or VIH. CE L L L H L L L L X X OE L L L X H H VID L X X H X X WE H H H X H L A0 L H A0 X X A0 L L X X A1 L L A1 X X A1 H H X X A6 L L A6 X X A6 L L X X A9 VID VID A9 X X A9 VID VID X X DQ15 to DQ0 RESET Code Code DOUT High-Z High-Z DIN X Code X High-Z H H H H H H H H VID L = Pulse input. See "s DC CHARACTERISTICS" for voltage levels. *1: Manufacturer and device codes are accessed via a command register write sequence. See "MBM29LV652UE Command Definitions Table". *2: Refer to the section on Sector Group Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V 10% *5: Also used for the extended sector group protection. 8 MBM29LV652UE90 MBM29LV652UE Command Definitions Table Command Sequence Read/Reset*1 Read/Reset*1 Autoselect Program Chip Erase Sector Erase Erase Suspend Erase Resume Set to Fast Mode Fast Program *2 Reset from Fast Mode *2 Extended Sector Group Protection *3 Query *4 HiddenROM Entry HiddenROM Program *5 HiddenROM Exit *5 Bus First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Write Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Cycles Req'd Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 3 4 6 6 1 1 3 2 2 XXXh F0h -- -- 55h 55h 55h 55h 55h -- -- 55h PD -- XXXh XXXh -- F0h 90h -- RA IA PA -- RD ID PD -- -- -- -- -- -- -- -- 55h 55h -- -- -- -- -- -- -- -- -- XXXh SA -- -- -- -- -- -- -- -- -- 10h 30h -- -- -- -- -- XXXh AAh XXXh XXXh AAh XXXh XXXh AAh XXXh XXXh AAh XXXh XXXh AAh XXXh XXXh B0h XXXh 30h -- -- XXXh A0h XXXh XXXh -- -- XXXh -- -- 80h 80h -- -- 20h -- -- XXXh AAh XXXh XXXh AAh XXXh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- XXXh AAh XXXh XXXh A0h XXXh 90h PA XXXh F0h*6 SPA -- 60h -- 55h 55h 55h 4 1 3 4 4 XXXh XXh 60h 98h SPA -- XXXh 40h -- 88h SPA -- -- PA XXXh SD -- -- PD 00h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- XXXh AAh XXXh XXXh AAh XXXh XXXh AAh XXXh XXXh A0h XXXh 90h *1 : Both of these reset commands are equivalent. *2 : This command is valid during FAST Mode. *3 : This command is valid while RESET = VID. *4 : The valid address are A6 to A0. *5 : This command is valid during HiddenROM mode. *6 : The data "00h" is also acceptable. 9 MBM29LV652UE90 Notes : * Address bits = X = "H" or "L" for all address commands except or Program Address (PA) and Sector Address (SA). * Bus operations are defined in "MBM29LV652UE User Bus Operations Table". * RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16 and A15 will uniquely select any sector. * RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. * SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. * HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL) * The system should be genarated the following address patterns : Word mode : 555h or 2AAh to addresses A10 to A0 Byte mode : AAAh or 555h to addresses A10 to A0, and A-1 * The command combinations not described in command Definitions table are illegal. 10 MBM29LV652UE90 MBM29LV652UE Sector Group Protection Verify Autoselect Codes Table Type Manufacturer's Code Device Code Sector Group Protection A21 to A17 X X Sector Group Addresses A6 VIL VIL VIL A1 VIL VIL VIH A0 VIL VIH VIL Code (HEX) 04h 22D7h 01h * *: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. Extended Autoselect Code Table Type Manufacturer's Code Device Code Sector Group Protection Code 04h 22D7h 01h DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 1 11 MBM29LV652UE90 s FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Table Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Size 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words Address Range 000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh (Continued) 12 MBM29LV652UE90 Sector Address SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Size 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words Address Range 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh (Continued) 13 MBM29LV652UE90 Sector Address SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Size 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words Address Range 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh (Continued) 14 MBM29LV652UE90 (Continued) Sector Address SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Size 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words 32K words Address Range 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh 370000h to 377FFFh 378000h to 37FFFFh 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3FFFFFh 15 MBM29LV652UE90 Sector Group Address Table Sector Group Address SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A19 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A18 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Group Size 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words 128K words Sectors SA0 to SA3 SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA31 SA32 to SA35 SA36 to SA39 SA40 to SA43 SA44 to SA47 SA48 to SA51 SA52 to SA55 SA56 to SA59 SA60 to SA63 SA64 to SA67 SA68 to SA71 SA72 to SA75 SA76 to SA79 SA80 to SA83 SA84 to SA87 SA88 to SA91 SA92 to SA95 SA96 to SA99 SA100 to SA103 SA104 to SA107 SA108 to SA111 SA112 to SA115 SA116 to SA119 SA120 to SA123 SA124 to SA127 16 MBM29LV652UE90 Common Flash Memory Interface Code Table Description Description A6 to A0 DQ15 to DQ0 Query-unique ASCII string 10h 0051h Erase Block Region 2 "QRY" Information 11h 0052h bit 15 to bit 0 : y = Sector 12h 0059h number Primary OEM Command Set 13h 0002h bit 31 to bit 16 : z = Size 02h: AMD/FJ standard type 14h 0000h (zx 256 Byte) Address for Primary Extended 15h 0040h Query-unique ASCII string Table 16h 0000h "PRI" Alternate OEM Command Set 17h 0000h (00h = not applicable) 18h 0000h Major version number, ASCII Address for Alternate OEM 19h 0000h Minor version number, ASCII Extended Table 1Ah 0000h Address Sensitive Unlock VCC Min (write/erase) 1Bh 0027h 00h = Required DQ7-DQ4: 1 V, Erase Suspend DQ3-DQ0: 100 mV 02h = To Read & Write VCC Max (write/erase) 1Ch 0036h Sector Protection DQ7-DQ4: 1 V, 00h = Not Supported DQ3-DQ0: 100 mV X = Number of sectors in per VPP Min voltage 1Dh 0000h group VPP Max voltage 1Eh 0000h Sector Temporary Typical timeout per single 1Fh 0004h Unprotection byte/word write 2N s 01h = Supported Typical timeout for Min size 20h 0000h Sector Protection Algorithm buffer write 2N s Number of Sector for Bank 2 Typical timeout per individual 21h 000Ah 00h = Not Supported sector erase 2N ms Burst Mode Type 00h = Not Supported Typical timeout for full chip 22h 0000h erase 2N ms Page Mode Type 00h = Not Supported Max timeout for byte/word write 23h 0005h 2N times typical ACC (Acceleration) Supply Minimum 24h 0000h Max timeout for buffer write 2N 00h = Not Supported, times typical DQ7-DQ4: 1 V, Max timeout per individual 25h 0004h DQ3-DQ0: 100 mV sector erase 2N times typical ACC (Acceleration) Supply Max timeout for full chip erase 26h 0000h Maximum N times typical 2 00h = Not Supported, 27h 0017h Device Size = 2N byte DQ7-DQ4: 1 V, Flash Device Interface 28h 0001h DQ3-DQ0: 100 mV description 29h 0000h Max number of byte in 2Ah 0000h multi-byte write = 2N 2Bh 0000h Number of Erase Block Regions 2Ch 0001h within device Erase Block Region 1 2Dh 007Fh Information 2Eh 0000h bit 15 to bit 0 : y = Sector 2Fh 0000h number 30h 0001h bit 31 to bit 16 : z = Size (zx 256 Byte) A6 to A0 31h 32h 33h 34h 40h 41h 42h 43h 44h 45h 46h 47h DQ15 to DQ0 0000h 0000h 0000h 0000h 0050h 0052h 0049h 0031h 0031h 0001h 0002h 0004h 48h 0001h 49h 4Ah 4Bh 4Ch 4Dh 0004h 0000h 0000h 0000h 00B5h 4Eh 00C5h 17 MBM29LV652UE90 s FUNCTIONAL DESCRIPTION Read Mode The MBM29LV652UE has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from "H" or "L". Standby Mode There are two ways to implement the standby mode on the MBM29LV652UE devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition the current consumed is less than 5 A Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = "H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L"). Under this condition the current consumed is less than 5 A Max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input. Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV652UE data. This mode can be used effectively with an application requesting low power consumption such as handy terminals. To activate this mode, MBM29LV652UE automatically switch themselves to low power mode when MBM29LV652UE addresses remain stable during access fine of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 A (CMOS Level). Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and MBM29LV652UE read-out the data for changed addresses. Output Disable With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. The Autoselect command may also be used to check the status of write-protected sectors (see "MBM29LV652UE Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in "s DEVICE BUS OPERATION"). This mode is functional over the entire temperature range of the devices. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON'T CARES except A0, A1, and A6. (See "MBM29LV652UE User Bus Operations Table" in "s DEVICE BUS OPERATION".) The manufacturer and device codes may also be read via the command register, for instances when the MBM29LV652UE is erased or programmed in a system without access to high voltage on the A9 pin. The 18 MBM29LV652UE90 command sequence is illustrated in "MBM29LV652UE Command Definitions Table" in "s DEVICE BUS OPERATION". (Refer to Autoselect Command section.) Word 0 (A0 = VIL) represents the manufacturer's code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device identifier code (MBM29LV652UE = 22D7h).These two words are given in the tables "MBM29LV652UE Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in "s DEVICE BUS OPERATION". All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See "MBM29LV652UE Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in "s DEVICE BUS OPERATION") In order to determine which sectors are write protected, A1 must be at VIH while running through the sector addresses; if the selected sector is protected, a logical `1' will be output on DQ0 (DQ0 = 1). Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The MBM29LV652UE features hardware sector group protection. This feature will disable both program and erase operations in any combination of thirty two sector groups of memory. (See "Sector Group Address Table" in "s FLEXIBLE SECTOR-ERASE ARCHITECTURE"). The sector group protection feature is enabled using programming equipment at the user's site. The device is shipped with all sector groups unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, and A17) should be set to the sector to be protected. "Sector Address Table" in "s FLEXIBLE SECTOR-ERASE ARCHITECTURE" defines the sector address for each of the one hundred twenty-eight (128) individual sectors, and "Sector Group Address Table" in "FLEXIBLE SECTOR-ERASE ARCHITECTURE" defines the sector group address for each of the thirty-two (32) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See " (11) Sector Group Protection Timing Diagram" in "s TIMING DIAGRAM" and " (15) Sector Group Protection Algorithm" in "s FLOW CHART" for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18, and A17) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the device will produce "0" for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON'T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A21, A20, A19, A18, and A17) are the desired sector group address will produce a logical "1" at DQ0 for a protected sector group. See "MBM29LV652UE Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in "s DEVICE BUS OPERATION". Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the MBM29LV652UE devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting 19 MBM29LV652UE90 the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to " (12) Temporary Sector Group Unprotection Timing Diagram" in "s TIMING DIAGRAM" and " (6) Temporary Sector Group Unprotection Algorithm" in "s FLOW CHART". This temporary sector group unprotect mode is disabled whenever the chip is in the HiddenROM mode. This area can not be programmed within this mode. Moreover once this area is programmed, it is always protected no matter in which mode. RESET Hardware Reset Pin The MBM29LV652UE devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional "tRH" before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Accelerated Program Operation MBM29LV652UE offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 50%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system uses fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode is not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the present sequence is used for programming and detection of completion during acceleration mode. Removing VACC from the ACC pin returns the device to normal operation. Do not remove VACC from the ACC pin while programming. See " (14) Accelerated Program Timing Diagram" in "s TIMING DIAGRAM". Erase opeation during Accelerated Program Operations is strictly prohibited. 20 MBM29LV652UE90 s COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect data values or writing them in the improper sequence will reset the devices to the read mode. "MBM29LV652UE Command Definitions Table" in "s DEVICE BUS OPERATION" defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be read from the address, and an actual data of memory cell can be read from the another address. Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read cycle from address XX01h returns the device code (MBM29LV652UE = 22D7h). All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address XX02h. Scanning the sector group addresses (A21, A20, A19, A18, and A17) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See "MBM29LV652UE User Bus Operations Table" in "s DEVICE BUS OPERATION".) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and also to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence. Word Programming The devices are programmed on a word-by-word basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), and DQ6 (Toggle Bit) or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. 21 MBM29LV652UE90 The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (See "Hardware Sequence Flags Table".) Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1" Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0" Only erase operations can convert "0"s to "1"s. " (1) Embedded ProgramTM Algorithm" in "s FLOW CHART" illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Chip Erase Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), and DQ6 (Toggle Bit). The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming) " (2) Embedded EraseTM Algorithm" in "s FLOW CHART" illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of "tTOW" from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on "MBM29LV652UE Command Definitions Table" in "s DEVICE BUS OPERATION". This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the "tTOW" time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 127). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing 22 MBM29LV652UE90 a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), and DQ6 (Toggle Bit) or RY/BY. The sector erase begins after the "tTOW" time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase " (2) Embedded EraseTM Algorithm" in "s FLOW CHART" illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The addresses are "Don't Care" when writting the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/BY output pin will be at High-Z and the DQ7 bit will be at logic "1" and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 23 MBM29LV652UE90 Extended Command (1) Fast Mode MBM29LV652UE has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to " (7) Extended Sector Group Protection Algorithm" in "s FLOW CHART".) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to " (7) Extended Sector Group Protection Algorithm" in "s FLOW CHART".) (3) Extended Sector Group Protection In addition to normal sector group protection, the MBM29LV652UE has Extended Sector Group Protection as extended function. This function enable to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A21, A20, A19, A18, and A17) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins), and write extended sector group protection command (60h). A sector group is typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A21, A20, A19, A18, and A17) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a logical "1" at device output DQ0 will produce for protected sector in the read operation. If the output data is logical "0", please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to " (13) Extended Sector Group Protection Timing Diagram" in "s TIMING DIAGRAM" and " (8) Embedded ProgramTM Algorithm for Fast Mode" in "s FLOW CHART".) (4) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ15 to DQ8) is "0" in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the read/reset command sequence into the register. (See "Common Flash Memory Interface Code Table" in "s FLEXIBLE SECTOR-ERASE ARCHITECTURE".) HiddenROM Region The HiddenROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is programmed, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The HiddenROM region is 128 words in length. After the system has written the Enter HiddenROM command sequence, it may read the HiddenROM region by using device addresses A6 to A0 (A14 to A7 are "00", A21 to A15 are don't care). That is, the device sends only program command that would normally be sent to the address to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the address. 24 MBM29LV652UE90 HiddenROM Entry Command MBM29LV652UE has a HiddenROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. HiddenROM area is 128words in length. Write the HiddenROM entry command sequence to enter the HiddenROM area. It is called as HiddenROM mode when the HiddenROM area appears. After the system has written the Enter HiddenROM command sequence, it may read the HiddenROM region by using device addresses A6 to A0 (A14 to A7 are "00", A21 to A15 are don't care). Read/program of the HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is same as the program command in the past except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. HiddenROM Protect Command There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command(60h), set the sector address to select (A6, A1, A0) = (0,1,0) and HiddenROM area and write the sector group protect command(60h) during the HiddenROM mode. Same command sequence could be used because other then the HiddenROM mode and that is does not apply high voltage to RESET pin, it is same as the extension sector group protect in the past. Please refer "Function Explanation Extended Command (3) Extentended Sector Group Protection" for details of extention sector group protect setting. The other is to apply high voltage (VID) to A9 and OE, specify the sector address to select (A6, A1, A0) = (0,1,0) and HiddenROM area, and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address to select the HiddenROM area, and read. When "1" appears to DQ0, the protect setting is completed. "0" will appear to DQ0 if it is not protected. Please apply write pulse agian. Same command sequence could be used for the above method because other then the HiddenROM mode, it is same as the sector group protect in the past. Please refer "Function Explanation Secor Group Protection" for details of sector group protect setting Once it is protected, protection can not be cancelled, so please pay closest attention. Write Operation Status Detailed in "Hardware Sequence Flags", all the status flags that can be used to check the status of the device for current mode operation. During sector erase, the part provides the status flags automatically to the I/O ports. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which sectors are erasing and which are not. Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. 25 MBM29LV652UE90 Hardware Sequence Flags Table Status Embedded Program Algorithm Embedded Erase Algorithm In Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 0 1 0 Data 0 0 1 0 DQ2 1 Toggle* Toggle Data 1* 1 N/A N/A *: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. Notes: * DQ0 and DQ1 are reserve pins for future use. * DQ4 is Fujitsu internal use only. DQ7 Data Polling The MBM29LV652UE devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in " (3) Data Polling Algorithm" in "s FLOW CHART". For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29LV652UE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See "Hardware Sequence Flags Table".) See " (6) Data Polling during Embedded Algorithm Operation Timing Diagram" in "s TIMING DIAGRAM" for the Data Polling timing specifications and diagram. 26 MBM29LV652UE90 DQ6 Toggle Bit I The MBM29LV652UE also feature the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 s and then stop toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. See Figure " (7) Toggle Bit I during Embedded Algorithm Operation Timing Diagram" in "s TIMING DIAGRAM" for the Toggle Bit I timing specifications and diagram. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in "MBM29LV652UE User Bus Operations Table" in "s DEVICE BUS OPERATION". The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the DQ5 bit will indicate a "1". Please note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence. DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Hardware Sequence Flags Table". DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. 27 MBM29LV652UE90 Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also "Toggle Bit Status Table" and " (8) DQ2 vs. DQ6" in "s TIMING DIAGRAM". Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. Reading Toggle Bits DQ6 /DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (See "Toggle bit algorithm" in "s FLOW CHART"). Toggle Bit Status Table Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle DQ2 1 Toggle*1 Toggle 1 *2 *1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. 28 MBM29LV652UE90 RY/BY Ready/Busy The MBM29LV652UE provide a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands. If the MBM29LV652UE is placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to " (9) RY/BY Timing Diagram during Program/Erase Operation Timing Diagram" and " (10) RESET, RY/BY Timing Diagram" in "s TIMING DIAGRAM" for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices can be connected via several RY/BY pins in parallel. Data Protection The MBM29LV652UE is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min). If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be a logical zero while OE is a logical one. Power-up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. Sector Protection Device user is able to protect each sector group individually to store and protect data. Protection circuit voids both write and erase commands that are addressed to protected sectors. Any commands to write or erase addressed to protected sector are ignored (See "Sector Group Protection" in "s FUNCTIONAL DESCRIPTION". 29 MBM29LV652UE90 s ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature with Power Applied Storage Temperature Voltage with respect to Ground All Pins except A9, OE, ACC and RESET *1, *2 Power Supply Voltage *1 A9, OE, ACC, and RESET *1, *3 Power Supply Voltage* 1 Symbol TA Tstg VIN, VOUT VCC VIN VCCq Rating Min - 40 - 55 - 0.5 - 0.5 - 0.5 - 0.2 Max + 85 + 125 VCC + 0.5 + 4.0 + 13.0 + 7.0 Unit C C V V V V *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or l/O pins is - 0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to - 2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9, OE, ACC and RESET pins is - 0.5 V. During voltage transitions, A9, OE, ACC, and RESET pins may undershoot VSS to - 2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCC) does not exceed + 9.0 V. Maximum DC input voltage on A9, OE, ACC, and RESET pins is + 13.0 V which may overshoot to + 14.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature Power Supply Voltage (VCC)* Power Supply Voltage (VCCq) Symbol TA VCC VCCq Value Min - 40 + 3.0 + 2.7 Max + 85 + 3.6 + 3.6 Unit C V V * : Voltage is defined on the basis of VSS = GND = 0 V. Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 30 MBM29LV652UE90 s MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.6 V -0.5 V -2.0 V 20 ns 20 ns 20 ns Maximum Undershoot Waveform VCC +2.0 V VCC +0.5 V 20 ns +2.0 V 20 ns 20 ns Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC +0.5 V 20 ns 20 ns Note: This waveform is applied for A9, OE, ACC, and RESET. Maximum Overshoot Waveform 2 31 MBM29LV652UE90 s DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current Symbol ILI ILO ILIT Test Conditions VIN = VSS to VCC, VCC = VCC Max, VCCq = VCCq Max VOUT = VSS to VCC, VCC = VCC Max, VCCq = VCCq Max VCC = VCC Max, A9 = OE = RESET = 12.5 V CE = VIL, OE = VIH, VCC = VCC Max, VCCq = VCCq Max, f = 5 MHz CE = VIL, OE = VIH, VCC = VCC Max, VCCq = VCCq Max, f = 1 MHz CE = VIL, OE = VIH, VCC = VCC Max, VCCq = VCCq Max VCC = VCC Max, VCCq = VCCq Max, CE = VCC 0.3 V, RESET = VCC 0.3 V VCC = VCC Max, VCCq = VCCq Max, RESET = VSS 0.3 V VCC = VCC Max, VCCq = VCCq Max, CE = VSS 0.3 V, RESET = VCC 0.3 V, VIN = VCC 0.3 V or VSS 0.3 V VCC = VCC Max, ACC = VACC Max -- -- -- -- IOL = 4.0 mA, VCC = VCC Min, VCCq = VCCq Min IOH = - 2.0 mA, VCC = VCC Min, VCCq = VCCq Min IOH = - 100 A, VCC Min, VCCq = VCCq Min -- Min - 1.0 - 1.0 -- -- -- -- -- -- Max + 1.0 + 1.0 35 16 7 40 5 5 Unit A A A mA mA mA A A VCC Active Current*1 ICC1 VCC Active Current*2 VCC Current (Standby) VCC Current (Standby, RESET) VCC Current (Automatic Sleep Mode)*5 ACC Accelerated Program Current Input Low Level Voltage Input High Level Voltage Voltage for Program Acceleration Voltage for Autoselect, Sector Protection (A9, OE, RESET)*3, *4 Output Low Voltage ICC2 ICC3 ICC4 ICC5 -- 5 A IACC VIL VIH VACC VID VOL VOH1 -- - 0.5 2.0 11.5 11.5 -- 2.4 VCCq - 0.4 2.3 20 0.6 VCC + 0.5 12.5 12.5 0.45 -- -- 2.5 mA V V V V V V V V Output High Voltage VOH2 Low VCC Lock-Out Voltage VLKO *1 : The lCC current listed includes both the DC operating current and the frequency dependent component. *2 : lCC active while Embedded Erase or Embedded Program is in progress. *3 : This timing is only for Sector Group Protection operation and Auto select mode. *4 : Applicable for only VCC applying. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *5 : Embedded Algorithm (program or erase) is in progress (@5 MHz) . 32 MBM29LV652UE90 s AC CHARACTERISTICS * Read Only Operations Characteristics Symbols Parameter JEDEC Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Address, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- Standard tRC tACC tCE tOE tDF tDF tOH tREADY -- CE = VIL, OE = VIL OE = VIL -- -- -- -- -- Test Setup Min 90 -- -- -- -- -- 0 -- Value (Note) Max -- 90 90 35 30 30 -- 20 ns ns ns ns ns ns ns s Unit Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29LV652UE90) Input rise and fall times: 5 ns Input pulse levels: 0.0 V or 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V 3.3 V Diode = 1N3064 or Equivalent Device Under Test 6.2 k CL Diode = 1N3064 or Equivalent 2.7 k Note : CL = 30 pF including jig capacitance (MBM29LV652UE90) Test Conditions 33 MBM29LV652UE90 * Write (Erase/Program) Operations Symbol Parameter JEDEC Standard Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Output Enable Hold Time Toggle and Data Polling Read Recover Time Before Write Read Recover Time Before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Word Programming Operation Sector Erase Operation*1 VCC Setup Time Rise Time to VID*2 Rise Time to VACC*3 Voltage Transition Time*2 Write Pulse Width*2 OE Setup Time to WE Active*2 CE Setup Time to WE Active*2 Recover Time From RY/BY RESET Pulse Width tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- -- -- -- -- tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP tCSP tRB tRP -- tOEH 10 0 0 0 0 0 0 35 35 30 30 -- -- 50 500 500 4 100 4 4 0 500 -- -- -- -- -- -- -- -- -- -- -- 16 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns s s s ns ns s s s s ns ns tAVAV tAVWL tWLAX tDVWH tWHDX -- tWC tAS tAH tDS tDH tOES Min 90 0 45 35 0 0 0 Typ -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- ns ns ns ns ns ns ns Value Unit (Continued) 34 MBM29LV652UE90 (Continued) Symbol Parameter JEDEC RESET Hold Time Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Suspend Transition Time Erase Time-out Time *1 : This does not include the preprogramming time. *2 : This timing is for Sector Group Protection operation. *3 : This timing is for Accelerated Program operation. -- -- -- -- -- Standard tRH tBUSY tEOE tSPD tTOW Min 200 -- -- -- 50 Typ -- -- -- -- -- Max -- 90 90 20 -- ns ns ns s s Value Unit 35 MBM29LV652UE90 s ERASE AND PROGRAMMING PERFORMANCE Limit Parameter Min Sector Erase Time Programming Time Chip Programming Time Erase/Program Cycle -- -- -- 100,000 Typ 1 16 -- -- Max 10 360 200 -- s s s cycle Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead -- Unit Comments s PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ 6.0 8.5 8.0 15.0 Max 7.5 12.0 10.0 20.0 Unit pF pF pF pF Note : Test conditions TA = + 25 C, f = 1.0 MHz 36 MBM29LV652UE90 s TIMING DIAGRAM * Key to Switching Waveforms WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L" Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is HighImpedance "Off" State (1) Read Operation Timing Diagram tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tCE tOH Outputs High-Z Output Valid High-Z 37 MBM29LV652UE90 (2) Hardware Reset/Read Operation Timing Diagram tRC Address tACC Address Stable CE tRH tRP tRH tCE RESET tOH Outputs High-Z Output Valid 38 MBM29LV652UE90 (3) Alternate WE Controlled Program Operation Timing Diagram 3rd Bus Cycle Address XXXh tWC tAS PA tAH Data Polling PA tRC CE tCS tCH tCE OE tGHWL tWP tWPH tWHWH1 tOE WE tDS tDH tDF tOH Data A0h PD DQ7 DOUT DOUT Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence. 39 MBM29LV652UE90 (4) Alternate CE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling PA tAS tAH PA Address XXXh tWC WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH Data A0h PD DQ7 D OUT Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence. 40 MBM29LV652UE90 (5) Chip/Sector Erase Operation Timing Diagram Address XXXh tWC XXXh tAS tAH XXXh XXXh XXXh SA * CE tCS tCH OE tGHWL tWP tWPH WE tDS AAh tDH 55h 80h AAh 55h 10h/ 30h Data tVCS VCC * : SA is the sector address for Sector Erase. Addresses = XXXh for Chip Erase. 41 MBM29LV652UE90 (6) Data Polling during Embedded Algorithm Operation Timing Diagram CE tCH tOE tDF OE tOEH WE tCE * DQ7 Data DQ7 DQ7 = Valid Data High-Z tWHWH1 or 2 DQ6 to DQ0 Data tBUSY DQ6 to DQ0 = Output Flag tEOE DQ6 to DQ0 Valid Data High-Z RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation.) (7) Toggle Bit I during Embedded Algorithm Operation Timing Diagram CE tOEH WE tOES OE tDH * = Toggle DQ6 DQ6 Data (DQ7 to DQ0) DQ6 = Toggle DQ6 = Stop Toggling tOE DQ7 to DQ0 Data Valid * : DQ6 = Stops toggling. (The device has completed the Embedded operation.) 42 MBM29LV652UE90 (8) DQ2 vs. DQ6 Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Toggle DQ2 and DQ6 with OE or CE Note : DQ2 is read from the erase-suspended sector. (9) RY/BY Timing Diagram during Program/Erase Operation Timing Diagram CE Rising edge of the last write pulse WE Entire programming or erase operations RY/BY tBUSY (10) RESET,RY/BY Timing Diagram WE RESET tRP tRB RY/BY tREADY 43 MBM29LV652UE90 (11) Sector Group Protection Timing Diagram A21, A20, A19 A18, A17 SPAX SPAY A0 A1 A6 VID VIH A9 tVLHT VID VIH OE tVLHT tWPP tVLHT tVLHT WE tOESP CE tCSP Data tVCS tOE 01h VCC SPAX = Sector Group Address to be protected SPAY = Sector Group Address to be protected 44 MBM29LV652UE90 (12) Temporary Sector Group Unprotection Timing Diagram VCC tVCS VID VIH RESET tVIDR tVLHT CE WE tVLHT RY/BY Unprotection period Program or Erase Command Sequence tVLHT 45 MBM29LV652UE90 (13) Extended Sector Group Protection Timing Diagram VCC tVCS RESET tVIDR Address tVLHT tWC tWC SPAX SPAX SPAX A6, A0 A1 CE OE tWP WE TIME-OUT Data 60h 60h 40h tOE 01h 60h SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min) 46 MBM29LV652UE90 (14) Accelerated Program Timing Diagram VCC tVCS VACC VIH ACC tVACCR tVLHT CE WE tVLHT Program Command Sequence tVLHT Acceleration period 47 MBM29LV652UE90 s FLOW CHART EMBEDDED ALGORITHMS Start Write Program Command Sequence (See below) Data Polling Embeded Program Algorithm in progress No Verify Data ? Yes Increment Address No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): XXXh/AAh XXXh/55h XXXh/A0h Program Address/Program Data (1) Embedded ProgramTM Algorithm 48 MBM29LV652UE90 EMBEDDED ALGORITHMS Start Write Erase Command Sequence (See below) Data Polling Embeded Program Algorithm in progress Data = FFh ? Yes Erasure Completed Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): XXXh/AAh No Chip Erase Command Sequence (Address/Command): XXXh/AAh XXXh/55h XXXh/55h XXXh/80h XXXh/80h XXXh/AAh XXXh/AAh XXXh/55h XXXh/55h XXXh/10h Sector Address/30h Sector Address/30h Additional sector erase commands are optional. Sector Address/30h (2) Embedded EraseTM Algorithm 49 MBM29LV652UE90 Start Read Byte (DQ 7 to DQ0) Addr. = VA DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA Yes VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = Any of the sector addresses within the sector not being protected during chip erase DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. (3) Data Polling Algorithm 50 MBM29LV652UE90 Start Read DQ7 to DQ0 Addr. = "H" or "L" *1 Read DQ7 to DQ0 Addr. = "H" or "L" DQ6 = Toggle? Yes No No DQ5 = 1? Yes *1,*2 Read (DQ7 to DQ0) Addr. = "H" or "L" *1,*2 Read (DQ7 to DQ0) Addr. = "H" or "L" DQ6 = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command No Program/Erase Operation Complete *1 : Reset toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit since it may stop toggle as DQ5 changes to "1". (4) Toggle Bit Algorithm 51 MBM29LV652UE90 Start Setup Sector Group Addr. (A21, A20, A19, A18, A17) PLSCNT = 1 OE = VID, A9 = VID, A6 = CE = VIL, RESET = VIH A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 s WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group (Addr. = SGA, A0 = VIL, A1 = VIH, A6 = VIL) No No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command Data = 01h? Yes Yes Protect Another Sector Group ? No Remove VID from A9 Write Reset Command Device Failed Sector Group Protection Completed (5) Sector Group Protection Algorithm 52 MBM29LV652UE90 Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1 : All protected sector groups are unprotected. *2 : All previously protected sector groups are protected once again. (6) Temporary Sector Group Unprotection Algorithm 53 MBM29LV652UE90 Start RESET = VID Wait to 4 s Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT =1 To Sector Group Protection Write SGA/60h (A0 = VIL, A1 = VIH, A6 = VIL) Time Out 250 s Setup Next Sector Group Address Increment PLSCNT To Verify Sector Group Protection Write SGA/40h (A0 = VIL, A1 = VIH, A6 = VIL) Read from Sector Group Address (A0 = VIL, A1 = VIH, A6 = VIL) No PLSCNT No Data = 25? = 01h? Yes Yes Yes Remove VID from RESET Write Reset Command Protection Other Sector Group? No Device Failed Remove VID from RESET Write Reset Command Sector Group Protection Completed (7) Extended Sector Group Protection Algorithm 54 MBM29LV652UE90 FAST MODE ALGORITHM Start XXXh/AAh XXXh/55h Set Fast Mode XXXh/20h XXXh/A0h Program Address/Program Data Data Polling Device Verify Data? Yes No No In Fast Program Increment Address Last Address ? Yes Programming Completed XXXh/90h Reset Fast Mode XXXh/F0h (8) Embedded ProgramTM Algorithm for Fast Mode 55 MBM29LV652UE90 s ORDERING INFORMATION Part No. MBM29LV652UE90PBT Package 63-pin plastic FBGA (BGA-63P-M02) Access Time (ns) 90 Remarks MBM29LV652U E 90 PBT PACKAGE TYPE PBT = 63-ball Fine pitch Ball Gind Array Package (FBGA) Standard Pinout SPEED OPTION See Product Selector Guide DEVICE REVISION DEVICE NUMBER/DESCRIPTION MBM29LV652U 64 Mega-bit (4M x 16-Bit) CMOS Flash Memory 3.0 V-only Read, Program, and Erase 56 MBM29LV652UE90 s PACKAGE DIMENSION 63-ball plastic FBGA (BGA-63P-M02) +0.15 +.006 11.000.10(.433.004) 1.05 -0.10 (8.80(.346)) (7.20(.283)) (5.60(.220)) 0.80(.031)TYP .041 -.004 (Mounting height) 0.380.10 (.015.004) (Stand off) 8 7 6 10.000.10 (.394.004) (4.00(.157)) (5.60(.220)) 5 4 3 2 1 M INDEX AREA L K J H G F E D C B A INDEX BALL 63-o0.450.05 (63-o0.18.002) 0.08(.003) M 0.10(.004) C 2001 FUJITSU LIMITED B63002S-c-3-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. 57 MBM29LV652UE90 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0305 (c) FUJITSU LIMITED Printed in Japan |
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